Layer 2 · TSM — TSMC ADR
One-line thesis
TSMC owns the only sub-5nm logic fab capacity that NVIDIA, AMD, Broadcom, Marvell, Apple, Qualcomm, MediaTek and the AI custom-silicon cohort can physically use to build product through 2027 — the cleanest, deepest moat in the cycle, with capex guided to the high end of $52-56B and the eighth straight beat-and-raise just confirmed.
What TSMC physically does
TSMC manufactures the leading-edge logic wafers — N5, N4P, N3E, N3P, and starting H2 2026 the N2 node with gate-all-around (GAA) nanosheet transistors — that every AI silicon design house ultimately depends on for production. The Hsinchu, Tainan, Kaohsiung, and increasingly Arizona and Kumamoto fabs collectively process roughly 90% of the world's sub-7nm wafers. NVIDIA Blackwell is N4P. NVIDIA Rubin is N3P moving to N2. AMD MI355X is N3E. Apple M5 / M6 and A19 / A20 are N3E moving to N2. Every meaningful AI silicon program — Google TPU, Meta MTIA, AWS Trainium, Microsoft Maia, the OpenAI Titan if/when it ships — is fabricated at TSMC. There is no alternative at the leading edge that can absorb material volume — Samsung Foundry's 3nm process has yield and customer-traction problems that have persisted for three years; Intel 18A is just beginning to ship pilot product; nobody else is close.
Beyond wafer manufacture, TSMC also owns the dominant advanced-packaging franchise — CoWoS-S (current AI workhorse for GPU + HBM stacking), CoWoS-L (Blackwell's 2-die reticle-stitched package), CoWoS-R (rumoured for Rubin), the InFO line for mobile, and the SoIC (System-on-Integrated-Chip) hybrid-bonding platform that will enable 3D logic-on-logic stacking from 2027 onward. CoWoS capacity has been the binding constraint on AI silicon supply for two years running; TSMC's stated capex ramp is meant to lift CoWoS-L monthly wafers from ~50k in 2025 to ~120k by end-2026 and approximately 200k by 2027.
For an AI-stack investor: TSMC is the upstream choke point. Every NVIDIA dollar, every Broadcom dollar, every Marvell dollar of AI silicon revenue first becomes a TSMC wafer-equivalent. The economics of the cycle ultimately settle into TSMC's ASP per wafer, capacity utilisation, and packaging mix.
The financial print
Q1 2026 (reported April 16 2026) printed $35.9B of revenue against $35.5B consensus — beat — at +40.6% YoY in USD terms. Non-GAAP EPS of $3.49 beat $3.26 consensus by 7.1%. This was the eighth consecutive quarter of revenue and EPS beats — a track record matched by essentially no other large-cap semiconductor company. Q1 gross margin printed 58.3%; AI HPC revenue dominated the wafer mix; the company maintained FY26 USD revenue growth guidance above 30%, and pushed full-year capex toward the high end of the $52-56B band — implying $14B+ of quarterly capex through the back half.
The April monthly revenue release (May 10 disclosure) showed NT$410.7B in April, +17.5% YoY, with YTD running +29.9%. Monthly data is the highest-frequency confirmation in the sector; the trend remains intact. The stock at $404 sits roughly 8% below the all-time high. 1m +9%, 3m +13%.
Q2 prints July 17. Consensus is $39-40B revenue and $3.85-4.00 EPS. The setup is similar to the AVGO setup — high consensus expectations into a print with strong monthly data behind it. The most likely surprise is on capex commentary: any uplift in the FY26 capex band toward $58-60B would be read positively by the equipment supply chain (KLAC, LRCX, AMAT, ASML, BESI, ONTO, CAMT) and would confirm the back-half AI ramp visibility.
Customer mix
Apple remains the single largest customer at approximately 22-24% of revenue (M-series Mac, A-series iPhone, M-series iPad). NVIDIA is now the second-largest customer and likely the fastest-growing, at approximately 18-20% of revenue and rising toward 25% on consensus FY27 modelling. AMD, Broadcom, Marvell, Qualcomm, MediaTek collectively contribute another 20-25%. The Chinese fabless cohort (HiSilicon residual, the new Huawei design teams) is now restricted under the US export regime and contributes <5%. The customer base is the most diversified in foundry — Apple's iPhone-cycle volatility, NVIDIA's AI cycle, AMD's PC and AI, and the broader mobile / consumer book all rotate through the same wafer mix.
The technology-node mix is what determines current margin. Q1 26 wafer revenue mix: 5nm-and-below (N5, N4, N3) at approximately 60% of revenue and rising; 7nm at approximately 15% (declining); 16nm and 28nm at the balance for legacy product. The high-performance computing platform — which captures all AI silicon — represented approximately 59% of Q1 26 wafer revenue, with smartphone at 28% (Apple, MediaTek, Qualcomm baseband), IoT at roughly 5%, automotive at 5%, and consumer at 3%. The HPC mix is unprecedented in TSMC's history (smartphone was the largest segment as recently as 2022) and is the principal driver of the gross margin uplift from 53% in 2023 to 58%+ in 2026.
Competitive context
There is no head-on competitor at the leading edge. Samsung Foundry's 3nm has not closed the yield gap and the principal large customers (Qualcomm Snapdragon, NVIDIA in any meaningful program) have all returned to TSMC after pilot runs at Samsung in 2023-25. Intel Foundry Services (18A) is now shipping pilot Panther Lake silicon and is taking external design wins (rumoured Microsoft, rumoured a defence customer) but is at least three years behind TSMC on volume and at least five on the packaging franchise. Chinese foundries (SMIC) are stuck at 7nm equivalent and barred from EUV imports.
The structural moat is the combination of process technology, packaging integration, and customer-design ecosystem (the OIP — Open Innovation Platform — which has standardised IP libraries across the leading-edge cohort). Even if Samsung or Intel close the process gap, the packaging franchise (CoWoS, SoIC) and the customer-design lock-in are 2-3 year minimum moves to displace. The customer-design ecosystem in particular is under-appreciated: TSMC ships hundreds of process-design-kits (PDKs), IP libraries, EDA tool integrations, and reference-design flows that every fabless customer integrates into its design methodology. Switching foundries means re-validating every IP block, every EDA tool flow, every signoff methodology — a 12-24 month engineering effort that even the largest customers do not undertake casually.
The CoWoS-L packaging franchise — the 2.5D interposer technology that bonds GPU dies to HBM stacks — is the additional moat. TSMC's CoWoS capacity has been the binding constraint on AI silicon supply for two consecutive years; the announced capacity ramp from ~50k wafers/month in 2025 to ~120k wafers/month by end-2026 to approximately 200k wafers/month by 2027 is itself a major industry story (driving equipment orders at KLAC, LRCX, AMAT, BESI, Onto, Camtek). Samsung's I-Cube competing packaging platform has won materially less customer commitment; Intel's Foveros 3D packaging is technically promising but lacks the customer ecosystem to compete at AI scale.
Terminal risk
The terminal risk is geopolitical, not commercial. A Chinese kinetic action against Taiwan would close the leading-edge logic supply chain for the duration of the conflict and force a 2-3 year disorderly re-organization of the global semiconductor map. This is the well-understood tail risk that supports an embedded geopolitical discount in the TSM multiple — typically 15-20% below where a peer-quality monopoly franchise would trade. The Arizona fabs (Phoenix Fab 1 in production, Fab 2 starting H2 26, Fab 3 announced for 2028) are the principal mitigant but are not yet at meaningful percentage of capacity. A 2027-28 Taiwan crisis scenario remains the principal risk-management variable for any TSM position.
Bull case
The base case is FY26 revenue of $130-138B (+30%+ YoY in USD), FY27 revenue of $160-175B (+25%), gross margin holding 56-58%, and the N2 ramp in H2 26 contributing materially through 2027. At a 26x forward — discount to NVDA, broadly in line with the high-quality compounder cohort — that prints the stock at $470-510 in 2027, +16-26% from spot.
The upside case is two-fold: capex guide raises through 2026 toward $60-65B annual run-rate (the equipment supply chain prices this in immediately); and the Arizona Fab 2 ramp accelerating in 2027, enabling US-domestic AI silicon volumes that allow TSMC to capture re-shoring premium pricing. That case prints the stock at $560-620 in 2027.
The pricing-power discussion is the underappreciated bull driver. TSMC has historically raised wafer prices 5-7% per year at the leading edge to recover the rising capex per wafer. The 2024-26 cycle has seen accelerated pricing — N3 wafer ASPs moved from ~$15k initially to closer to $22-25k by Q1 26, with reports of Apple and NVIDIA paying premiums above standard pricing for guaranteed capacity allocation. If the N2 generation prices at 15-20% above N3 (consistent with capex per wafer), and if AI HPC customers continue to pay incremental premium for CoWoS-L capacity allocation, the gross margin trajectory through 2027 is materially above current consensus 56-58%.
The Arizona fab is the secondary leg of the upside case. Fab 1 is in production with limited volume; Fab 2 starting H2 26 is expected to reach 100k wafers/month at N3 by end-2027; Fab 3 announced for 2028 will produce N2 silicon. Once US-domestic AI silicon volumes ramp materially in 2027-28, TSMC is positioned to capture re-shoring premium pricing from NVIDIA, Apple, Broadcom, AMD, and the DoD-adjacent customer set. The Arizona capacity is also the principal mitigant against the Taiwan-strait geopolitical risk, and as that capacity grows the embedded geopolitical discount in TSM's multiple should compress.
Gap / bear case
Two concerns the market may be missing. First, Q2 26 capex commentary may include a moderation signal if Apple iPhone demand softens — Apple is still the largest customer and Q2 typically reflects iPhone build commitments. Second, the FY27 gross margin trajectory depends on N2 ramp yields holding above the 50% bring-up threshold by H2 27 — if N2 yield trajectory slips, gross margin compresses sequentially through 2027 and the multi-year compounding case takes a haircut.
The third concern is the consensus PT setup: TSM PTs are now broadly $480-520, meaning the stock has roughly 20% upside to consensus — generous but not extreme — and a Taiwan-strait headline event remains the principal tail risk.
Optionality
Three options under-priced in consensus. CoWoS-L capacity expansion above guided run-rate in late 2026 (every AI silicon house is asking for more), which directly accretes to the equipment cohort but also lifts TSMC ASP per wafer. SoIC adoption ramping in 2027-28 for hybrid-bonded 3D logic — the first credible volume case is Apple M-series with stacked DRAM around 2027, plus the rumoured NVIDIA Rubin Ultra SoIC variant. And the long-tail option: a Saudi or UAE sovereign-AI capacity buildout that commits to a dedicated TSMC fab outside Taiwan, sometime in 2027-28.
The trade
TSM — BUY 9/10. Entry: starter at $400-410 spot; full-size on $370-385 pullback if a Taiwan-strait headline or broader semi correction creates entry. Position size: 4-5% of NLV — pair-trade tier with NVDA as the two-name core of any AI cycle exposure. Stop: daily close below $345 (200-day MA breach plus reversal of the post-Q1 rally). Catalyst date: July 17 Q2 print; June monthly rev release in early July; ongoing monthly data; N2 ramp commentary in H2 26. Trim/exit triggers: monthly revenue YoY growth below +15% on a single month; capex guide cut below $52B; any verifiable Apple or NVIDIA leakage to Samsung or Intel. Conviction: the highest-quality compounder in the semiconductor universe, with the most defensible moat. The reason this is 9/10 not 10/10 is the geopolitical tail — at $405 the equity already prices that risk at roughly a 20% discount to a hypothetical Texas-located analogue, but the tail is fat enough that conviction cannot exceed 9/10.