★ Research deep dive · AI Master Research · Tier A

Micron Technology · MU

2,161 words · sourced from AI Master Research. The full Photoncap-template treatment is below; the institutional PDF is downloadable.

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AI Master Research
Tier A · 2,161 words

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Layer 4

Layer 3 · MU — Micron Technology

One-line thesis

Best US-listed HBM pure-play running at 3x prior-year revenue with HBM sold out through 2027 — own it for the operating-leverage print into a memory super-cycle that consensus is still 12 months behind on.

What Micron physically does

Micron is one of three companies on the planet that can manufacture leading-edge DRAM at scale — alongside SK Hynix and Samsung — and one of the four that still matter in NAND. Inside the AI stack the relevant business is High Bandwidth Memory: 3D stacks of 8 to 16 DRAM dies bonded vertically onto a logic base die, threaded with thousands of through-silicon vias that pipe data into a GPU at multi-TB/s bandwidths. Every Blackwell, every B300, every MI355X, every Trainium chip ships with HBM bolted onto its package. You cannot ship more AI silicon than you can ship HBM, and Micron is the only American name in that triumvirate.

Physically, Micron fabricates the DRAM die in Boise, Hiroshima, Taichung and now Idaho — runs the wafers through TSV etch, thinning and stacking — and then ships finished HBM3E 8-Hi / 12-Hi modules to Nvidia, AMD, Broadcom and the hyperscalers' captive ASIC programs. Micron sits at Layer 3 of the AI stack — the memory layer — where the binding constraint of the entire compute economy currently lives. The Idaho IPF1/IPF2 greenfield expansion, supported by US CHIPS Act funding and several billion of customer prepayments, is the multi-year capacity vehicle. The Taichung HBM2E/3 expansion is the near-term volume engine. The Hiroshima 1-gamma node ramp is the technology lever for HBM4.

The thing to internalise about Micron is that it is not a memory cyclical anymore — at least not in the way the last twenty years taught investors to model it. HBM is sold under multi-year long-term agreements with fixed pricing into 2027. The commodity DRAM line remains cyclical, but the HBM line is structurally contracted, and HBM is now the majority of incremental revenue and almost all of incremental gross profit. The structural break from the historical Micron pattern — the four-year boom-bust DRAM cycle that returned 40% to shareholders one year and -30% the next — is that HBM contracts are now written more like aerospace supplier agreements than commodity-memory POs: take-or-pay, fixed-price escalators, multi-year volume commitments with non-cancellable deposits.

The HBM3E ramp through 2024-25 and the HBM4 production qualification cycle through 2026 are running ahead of consensus modelling. Micron's HBM3E 12-Hi is qualified at Nvidia Blackwell, and the HBM4 8-Hi/12-Hi samples have been delivered to lead customers for production qualification ahead of the Rubin platform launch. The technology roadmap to HBM4E and HBM5 is intact, with the 1-gamma node providing the bit-density step required to keep pace with Hynix on per-stack capacity. The Idaho fab is the geographic insurance against any single-site disruption risk, which is itself a hyperscaler procurement priority.

The financial print

Q2 FY26 (March quarter, reported March 20) printed $23.86 billion of revenue — roughly three times the prior-year quarter — and beat consensus on every line. Q3 guidance came at ~$33.5 billion, which is itself above the high end of Street consensus and was raised again in mid-cycle commentary. Gross margins are running in the high-50s%, operating margins comfortably above 40%. FY26 EPS consensus has now reset to $58 against $8.29 in FY25 — a seven-fold step-up in earnings power that the sell-side modelled to $20 just six months ago and which the buy-side is still adjusting position size against.

The stock closed $803.63 on May 14 and is up roughly +180% year-to-date. The Motley Fool $2,000 twelve-month target circulated May 11 is not as outlandish as the headline reads — it bakes in the consensus HBM TAM expansion from $35 billion in 2025 to roughly $100 billion in 2028, applies a normalised peer multiple, and works backward. The base case at consensus FY27 EPS of ~$70-80 and a 25x multiple lands you at $1,750-2,000 even without the optionality. Q3 FY26 reports June 25 — the next discrete catalyst.

The earnings-power math deserves an additional dimension. Micron's revenue per wafer-out on HBM is roughly 4-5x the revenue per wafer-out on commodity DRAM, and the gross profit per wafer is 7-9x higher because the HBM contribution margin is structurally higher. As the HBM mix moves from ~30% of revenue in FY26 to a consensus ~50% in FY27 and a stretch case 60%+ in FY28, the consolidated gross-margin trajectory is mechanically upward irrespective of commodity DRAM pricing. That is the lever that turns Micron from a cyclical $8-25 EPS business through the historical cycle into a $50-100 EPS business through the AI cycle.

Customer mix

Hyperscaler concentration is high and tightening rather than diversifying. Nvidia is the largest single buyer of Micron HBM3E by a wide margin — the B200/B300/Rubin pipeline runs on Micron and SK Hynix as the qualified vendors, with Samsung still working through HBM3E qualification — and that single customer is probably 25-35% of incremental HBM revenue in FY26. AMD's MI355X and MI400 pulls represent the next-largest tranche. AWS Trainium, Microsoft Maia and Google's next-generation TPU programs each take meaningful HBM volume directly or through their custom-silicon partners.

The customer book is heavily contracted into 2027 via LTAs that lock both price and volume. Management commentary from the March print explicitly said Micron can only meet 50-66% of medium-term demand — translation: the order book is bigger than the wafer plan, customers are paying upfront to secure allocation, and pricing is being negotiated at fixed escalators rather than spot. That is the kind of customer mix that produces operating margin expansion through a cycle, not compression at the peak.

Competitive context

The competitive set is two names: SK Hynix and Samsung. SK Hynix is the share leader in HBM3E and the first to qualify HBM4 with Nvidia — the structural #1 in the memory bottleneck. Micron is the credible #2 with the cleanest US-listed exposure, the fastest HBM3E qualification cycle Nvidia has ever run, and the cleanest balance-sheet improvement. Samsung is the laggard — HBM3E Nvidia qualification has been pending for over eighteen months, foundry losses persist, and the captive-fab structure makes it the slow mover.

Micron's moat is three-pronged. First, the technology gap on 1-beta/1-gamma DRAM nodes is narrow but real — Micron is roughly one node behind Hynix, ahead of Samsung. Second, the customer relationships are sticky because HBM qualification cycles are 12-18 months, which means a customer who has qualified Micron does not lightly switch back. Third, the US-listed wrapper plus CHIPS Act geography gives Micron a structural advantage for any hyperscaler that wants supply-chain diversification away from Korean concentration risk. The competitive context is a duopoly-plus-laggard rather than a true three-way race, and Micron sits inside the duopoly.

The pricing-power signature inside the competitive set is captured in the recent contract structure. Through 2023-24, HBM pricing was negotiated quarterly and pricing power belonged primarily to the customer. Through 2025, HBM pricing migrated to annual contracts. Through 2026, HBM is being sold on multi-year LTAs with non-cancellable structure and pricing escalators that favour the supplier. Micron has captured this transition fully — the visibility into 2027 is unprecedented for a DRAM business — and the marginal pricing leverage now sits with Micron, Hynix and Samsung rather than with the GPU vendors. That is a structural shift in the memory food chain that is not yet reflected in consensus through-cycle margin assumptions.

Terminal risk

The terminal risk is the same risk that has killed every memory bull case since 1995: the cycle peaks, new capacity ships, and pricing breaks. If Samsung's HBM4 qualification at Nvidia clears in H2 2026 and Samsung adds 50% to its HBM capacity as guided, the marginal HBM bit ships into a softer pricing environment in 2027. The bear scenario is FY27 revenue holding flat while gross margins compress 800-1000 bps, EPS halves, and the stock multiple compresses against a lower forward number — a classic memory cycle peak.

Bull case

The three-to-five-year bull case rests on the HBM TAM compounding from $35 billion in 2025 to $100 billion in 2028 and Micron holding 20-25% share — call it $20-25 billion of HBM revenue alone at peak, against $30 billion of HBM-eligible capacity supply and $80-100 billion of total Micron revenue. Operating margins in the high-30s structurally rather than the high-teens through-cycle averages of the last decade. FY28 EPS in the $90-110 range. A 20-25x multiple lands the stock at $1,800-2,750.

The bull case also includes the optionality on HBM4E and HBM5 generations — where the 1-gamma node and Micron's R&D pipeline arguably narrow the gap to Hynix — and on the HBF (High Bandwidth Flash) joint roadmap with SanDisk and Kioxia, where AI inference storage becomes a structurally tight market in the late-2020s. Each of these is a free option at current prices.

The cash-generation arithmetic is what makes this an institutional rather than a retail trade. At consensus FY27 EBITDA of $35-40 billion and capex running $15-17 billion through the Idaho ramp, free cash flow lands in the $18-25 billion range — enough to retire most of the legacy debt, run a meaningful buyback, and initiate a sustainable dividend. The transition from "memory cyclical with reinvestment needs" to "AI-memory franchise with capital-return capacity" is the re-rating mechanism that pulls multiple from the historic 8-12x forward through-cycle range to the 20-25x range that durable secular growers earn. Most sell-side models still anchor on the historical multiple band, which is the consensus error.

Gap / bear case

The market is right about the direction but probably still wrong about the magnitude. Consensus FY26 EPS at $58 still leaves room — sell-side has been chasing the number quarterly and is now structurally behind the LTA disclosures. But the gap the market may also be missing is on the downside: if 2027 is the cycle peak rather than the mid-cycle, and the LTAs reset lower from 2028 onwards, the stock that printed +180% YTD into the print could give back 40-50% in a six-month period. The bear case is not absent — it is delayed by 12-18 months. The asymmetry today still favours long; the asymmetry in mid-2027 may not.

The specific signal to watch for the cycle-peak inflection is HBM ASP movement in the monthly Trendforce and DRAMeXchange data, combined with hyperscaler capex guidance at the Q1 2027 prints. If hyperscaler capex guides flat or down for 2028 against 2027 levels, the LTA structure will hold short-term but the renewal terms in 2028-29 will reset materially lower. The historical memory-cycle peak pattern has been six to nine months of warning signs before the stock breaks; watching the ASP data carefully is the protective discipline.

A more granular signal worth watching is Samsung's HBM3E and HBM4 qualification track at Nvidia. If Samsung clears qualification in H2 2026 and ramps aggressively in 2027, Micron's HBM share at Nvidia could give back 200-400 basis points to Samsung, partially offsetting the volume growth. The mitigation is that the HBM TAM is growing fast enough that Micron's absolute HBM revenue continues to expand even at a lower share; but the share-loss optics would compress the multiple. Watching Samsung's qualification disclosures at quarterly print cycles is part of the trade discipline.

Optionality

Three free options worth tagging. First, HBF — High Bandwidth Flash — is a NAND-based AI inference tier that Micron is positioned alongside SanDisk and Kioxia to develop; this becomes a real TAM line if AI inference economics shift from training-dominated to inference-dominated, which is the current trajectory. Second, on-package memory for CPUs is an emerging architecture that Micron's LPDDR5X and 3DS DRAM products are uniquely positioned for as the GB-class CPU+GPU hybrid socket gains share. Third, the Idaho fab geography is itself a strategic option for US-DoD and US-cloud sovereign workloads — none of which is currently priced.

The trade

Entry: $760-820 — current zone is acceptable; on a 10-15% pullback to $700 is a clean add. Size: 4-5% portfolio weight target, scale on prints. Stop: $620 (close below 200-day MA invalidates). Catalyst date: Q3 FY26 print June 25, 2026. Trim/exit: trim 25% above $1,200; exit at $1,500 or on HBM ASP roll-over in 2027 monthly data. Conviction: 9/10.


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